Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
The principle way of reducing contact resistances between polysilicon gates and source/drain regions and interconnect lines is by forming metal silicides atop the source/drain regions and the gate electrodes prior to application of the conductive film for formation of the various conductive interconnect lines. Among the most common metal silicide materials are nickel silicide and cobalt silicide, typically formed by a salicide (self-aligned silicide) process. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps, for example at a temperature of 700° C. or higher. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the un-reacted metal is removed and an interconnect process is performed to provide conductive paths, such as by forming via holes through a deposited interlayer dielectric and filling the via holes with a conductive material, e.g., tungsten.
The conventional silicidation process, however, suffers drawbacks. For example, commonly used nickel silicide has a low resistivity and can be formed at a low temperature. However, it is sensitive to the high temperatures of subsequent processes, such as the formation of highly stressed CESL and/or ILD layers. Undesired effects such as stringers and encroachments may occur at the source/drain regions in the silicidation process and the effects are pronounced if nickel silicide alone is implemented. The function and reliability of the integrated circuit is thus adversely affected. Cobalt silicide, on the other hand, is more stable at high temperatures and the manufacturing process is more mature, thus is less likely to be adversely affected by the subsequent processes adopting high temperatures. However, it has a significant resistivity roll-off at dimensions of about 35 nm or below, meaning that its resistivity significantly increases when the dimension of the cobalt silicide features reach about 35 nm or lower. Since the gate of a MOS device typically has a smaller dimension than the respective source/drain regions, the resistivity roll-off will be observed on the gate silicide region first. This limits the usage of cobalt silicide in advanced technologies with small scales.
Accordingly, what is needed in the art is a new method and structure that may incorporate silicides to take advantage of the benefits associated with reduced resistivity while at the same time overcoming the deficiencies of the prior art.